I am a principal scientist in the Research & Development organisation of A.P. Møller-Mærsk.
My primary research interests are general aspects of computational statistics, measurement error models, missing data and causal inference with applications in logistics.
PhD in Biostastics, 2011
University of Copenhagen, Department of Biostatistics
MSc in Mathematics, 2006
University of Copenhagen, Department of Mathematics
Logic gates are the building blocks of digital electronics. Simple logic gates are efficiently implemented in various IC packages such as the 74HCXX series. However, it is educational to have a look at the implementation using just NPN transistors.
The 74HC165 and 74HC495 are useful integrated circuits for dealing with multiple digital inputs and outputs. In a recent project, I used the following prototype based on a variant of the above simple circuit schema:
The four 74HC495 ICs gives access to 2 x 16 bits accessible through IDC connectors controllable using just three pins on the microcontroller (DATA, CLOCK, LATCH). Similarly, two 74HC165 ICs gives access to 16 input bits through another IDC connector.
A small illustration on using the armadillo
C++ linear algebra
library for solving an ordinary differential equation of the form
\[ X’(t) = F(t,X(t),U(t)).\]
The abstract super class Solver
defines the methods solve
(for approximating the solution in
user-defined time-points) and solveint
(for interpolating user-defined
input functions on finer grid). As an illustration a simple
Runge-Kutta solver is derived in the class RK4
.
The first step is to define the ODE, here a simple one-dimensional ODE \(X’(t) = \theta\cdot\{U(t)-X(t)\}\) with a single input \(U(t)\):
rowvec dX(const rowvec &input, // time (first element) and additional input variables
const rowvec &x, // state variables
const rowvec &theta) { // parameters
rowvec res = { theta(0)*theta(1)*(input(1)-x(0)) };
return( res );
}
The ODE may then be solved using the following syntax
odesolver::RK4 MyODE(dX);
arma::mat res = MyODE.solve(input, init, theta);
with the step size defined implicitly by input
(first column is the time variable
and the following columns the optional different input variables) and
boundary conditions defined by init
.
Assume that two positive numbers are given, \(X\) and \(Y\), with unknown joint probability distribution \(P\), and \(X\neq Y\) a.s.
A player draws randomly one of the numbers and has to guess if the number is smaller or larger than the other unrevealed number, i.e., let \(U\sim Bernoulli(\tfrac{1}{2})\) independent of \(X, Y\), then the player sees \(Z_{1} = UX + (1-U)Y,\) and \(Z_{2} = (1-U)X + UY\) remains unseen.
A random guess (coin-flip) would due to the sampling \(U\), indepedently of \(F\), have probability \(\tfrac{1}{2}\) of correct guessing. The question is if we can find a better strategy?
The 74HC595: an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.
If higher load is required there is also the TPIC6C595 (e.g., for driving LEDs), or it should be paired with for example ULN2803 or similar. For multiple inputs see the 74HC165.
The basic usage is to serially transfer a byte from a microcontroller to the IC. When latched the byte will then in parallel be available on output pins QA-QH (Q0-Q7).
\(\newcommand{\pr}{\mathbb{P}}\newcommand{\E}{\mathbb{E}}\) Relative risks (and risk differences) are collapsible and generally considered easier to interpret than odds-ratios. In a recent publication Richardson et al (JASA, 2017) proposed a new regression model for a binary exposure which solves the computational problems that are associated with using for example binomial regression with a log-link function (or identify link for the risk difference) to obtain such parameter estimates.
Let \(Y\) be the binary response, \(A\) binary exposure, and \(V\) a vector of covariates, then the target parameter is
\begin{align*} &\mathrm{RR}(v) = \frac{\pr(Y=1\mid A=1, V=v)}{\pr(Y=1\mid A=0, V=v)}. \end{align*}
Let \(p_a(V) = \pr(Y \mid A=a, V), a\in\{0,1\}\), then the idea is to posit a linear model for \[ \theta(v) = \log \big(RR(v)\big) \] and a nuisance model for the odds-product \[ \phi(v) = \log\left(\frac{p_{0}(v)p_{1}(v)}{(1-p_{0}(v))(1-p_{1}(v))}\right) \] noting that these two parameters are variation independent which can be from the below L’Abbé plot. Similarly, a model can be constructed for the risk-difference on the following scale \[\theta(v) = \mathrm{arctanh} \big(RD(v)\big).\]
The 74HC165 is an 8-bit parallel-load or serial-in shift register.
Wiring:
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. CLK INH can be wired to GND to save a pin on the microcontroller. Unused inputs pins should be grounded as well.
Multiple 74HC165 ICs can be daisy chained by wiring the serial-out pin 9 (QH) to pin 10 (SER) of the succeeding IC allowing us to tie multiple 74165 ICs together that can be controlled using only 3 pins.